The present invention relates to a semiconductor circuit including a buffer circuit formed of MOS transistors.
Static memories which are formed of MOS transistors and have capable of operating at high speed are recently been developed. The operating speed of the static memories of this type is becoming almost equivalent to that of a memory formed of bipolar transistors. The operating speed of the static memory of this type is mainly improved by reducing the size of the MOS transistors or changing the circuit design in order to reduce the stray capacitance inherent in the MOS transistors. However, when these measures are taken with the static memories of this type, power consumption increases with higher operating speeds. In order to prevent an increase in power consumption, it is conventionally proposed to use a memory system in which the stand-by mode and the active mode can be selectively set. FIG. 1 shows an example of an address buffer circuit used in the static memory of this type. The buffer circuit shown in FIG. 1 has serially connected inverters 1 to 3 which are respectively formed of MOS transistors TR1 to TR3; TR4 to TR6; and TR7 to TR9, the current paths of which are connected in series between power source terminals VD and VS.
The MOS transistors TR1, TR4 and TR7 are of intrinsic type (I-type) wherein the threshold voltage of each transistor is substantially 0 V. The MOS transistors TR2, TR5 and TR8 are of depletion type (D-type). The MOS transistors TR3, TR6 and TR9 are of enhancement type (E-type).
The junction of the MOS transistors TR2 and TR3 is connected to the gate of the MOS transistor TR6. The junction of the MOS transistors TR5 and TR6 is connected to the gates of the MOS transistors TR9, TR10 and TR11 as well as to the power source terminal VS through an E-type MOS transistor TR12. The junction of the MOS transistors TR8 and TR9 is connected on one hand to the gate of an E-type MOS transistor TR13. The drain of that transistor is connected to the power source terminal VD through the D-type MOS transistor TR10 and the source of which is connected to the power source terminal VS. The junction of TR8 and TR9 is also connected to the gate of a D-type MOS transistor TR14. The drain of TR14 is connected to the power source terminal VD and the source of TR14 is connected to the power source terminal VS through the E-type MOS transistor TR11. The junction of the MOS transistors TR8 and TR9 is also connected to the power source terminal VS through an E-type MOS transistor TR15.
D-type MOS transistors TR16 and TR17 are connected parallel to the MOS transistors TR10 and TR14. The junction of the MOS transistors TR10 and TR13 and the junction of the MOS transistors TR11 and TR14 are respectively connected to output terminals A1 and A0 which are connected to a decoder circuit (not shown) having a great stray capacitance.
With the address buffer circuit shown in FIG. 1 in the stand-by mode, a chip selection signal CS of level "0" is supplied to the gates of the MOS transistors TR1, TR4 and TR7, and a chip selection signal CS of level "1" is supplied to the gates of the MOS transistors TR12, TR15, TR16 and TR17. Then, the MOS transistors TR1, TR4, TR7, TR11 and TR13 are rendered nonconductive, and the current paths of the inverters 1, 2 and 3 are cut off. Simultaneously, the output terminals A1 and A0 are respectively pulled up to the VD level through the MOS transistors TR16 and TR17. In this manner, in the stand-by mode, the current hardly flows through the buffer circuit and power consumption is reduced to the minimum.
In the active mode of this address buffer circuit, since the chip selection signals CS and CS of levels "1" and "0" are available, the MOS transistors TR1, TR4, and TR7 are rendered conductive. In response to an address input signal AIN applied to the gate of the MOS transistor TR3, address output signals are generated from the address output terminals A1 and A0.
In this address buffer circuit, power consumption in the active mode is reduced to the minimum by adopting a push-pull output circuit. However, since the MOS transistors TR10 and TR14 are of D-type, a considerably great current flows therethrough, resulting in large power consumption.
An address buffer circuit shown in FIG. 2 is basically the same configuration as that shown in FIG. 1 except that the D-type MOS transistors TR16 and TR17 are eliminated, and E-type MOS transistors TR18 and TR19 are respectively connected in parallel to the MOS transistors TR13 and TR11, and MOS transistors TR20 and TR21 are respectively connected between the power source terminal VD and the MOS transistors TR10 and TR14. In the active mode, the MOS transistors TR20 and TR21 are rendered conductive, while the MOS transistors TR18 and TR19 are rendered nonconductive. This address buffer circuit operates in the same manner as that shown in FIG. 1. In the stand-by mode, the MOS transistors TR18 and TR19 are rendered conductive, and the MOS transistors TR20 and TR21 are rendered nonconductive, so that the output terminals A1 and A0 are kept at the VS level. In this address buffer circuit, current flows through the MOS transistors TR10 and TR14 and power consumption increases in the active mode as in the case of the address buffer circuit shown in FIG. 1.
FIG. 3 shows an address buffer circuit in which the power consumption in the active mode is reduced. This address buffer circuit is of similar configuration to that shown in FIG. 2 except that in place of the MOS transistors TR10 and TR20, an I-type MOS transistor is used, the gate of which is connected to the junction of the MOS transistors TR5 and TR6 and the current path of which is connected between the MOS transistor TR13 and the power source terminal VD. Also in place of the MOS transistors TR14 and TR21, an I-type MOS transistor TR23 is used, the gate of which is connected to the junction of the MOS transistors TR8 and TR9 and the current path of which is connected between the MOS transistor TR11 and the power source terminal VD. In the active mode of this address buffer circuit, a gate signal of a phase opposite to that applied to the MOS transistors TR11 and TR22 is applied to the MOS transistors TR13 and TR23. Therefore, the steady state current hardly flows to the output circuit and the power consumption is reduced to the minimum. However, since the mutual conductance of the I-type MOS transistors is smaller than that of the D-type MOS transistors, it is necessary to set, to an extremely great value, a ratio W/L (where W and L indicate the channel width and channel length, respectively, of the I-type MOS transistors) in order to obtain the mutual conductance equivalent to that of the D-type MOS transistors. In order to do so, it is necessary to incorporate the large-sized inverters 1 to 3 for driving the I-type MOS transistors TR22 and TR23. As a consequence, a large current flows to these inverters 1 to 3 and the power consumption may not be suppressed to the minimum.